The present invention relates to a technique for manufacturing a semiconductor integrated circuit device, and particularly, to a technique which can effectively be used for manufacturing a semiconductor integrated circuit device, including a step of polishing a thin film formed on a surface of a semiconductor wafer with use of CMP (Chemical Mechanical Polishing).
The chemical mechanical polishing is a new micro processing technique involved by high integration and high performance of a semiconductor integrated circuit device (LSI). For example, this technique is adopted to formation of an element separation groove called SGI (Shallow Groove Isolation) and flattening of an interlayer insulating film in a multi-layered wire forming step and forming of an imbedded metal wiring. This chemical mechanical polishing is described, for example, in U.S. Pat. No. 4,944,836.
The chemical mechanical polishing is a method in which the surface of a wafer is polished while supplying polishing slurry onto a surface plate to which a polishing pad made of hard resins is adhered. Used as the polishing slurry is a resultant obtained by dispersing micro grains of a polishing agent such as silica (silicon oxide) or the like in pure water and by adding alkali for adjusting pH thereto. Known as silica contained in the polishing slurry are fumed silica (aerosol silica) obtained by burning silicon tetrachloride (SiCl4) and colloidal silica obtained from sodium silicate as a raw material (xe2x80x9cThe Science of CMPxe2x80x9d, pages 128 to 142, issued from Kabushiki-Kaisha Science Forum, Jul. 19, 1999).
Japanese Patent Laid-Open Publication No. 10-163284 discloses a wafer surface inspection method for determining whether the number of particles is the number of actual particles or the number including a scratch when particles remaining on the wafer surface after chemical mechanical polishing and cleaning processing are counted by a particle counter.
Recently, chemical mechanical polishing for LSI is carried out through a plurality of steps in a wafer process, in order to promote downsizing of elements and multi-layering. For example, in a step of forming an element separation groove in the main surface of a wafer, firstly, the main surface of the wafer is dry-etched, using an oxidation resistant insulating film as a mask, thereby to form a groove in the element separation region. Subsequently, a silicon oxide film having a greater film thickness than the depth of the groove is formed on the main surface of the wafer, and thereafter, the silicon oxide film is subjected to chemical mechanical polishing, using the oxidation-resistant insulating film as a stopper for polishing, so that the silicon oxide film selectively remain inside the groove. An element separation groove is thus formed. Also, in a step of flattening an inter-layer insulating film between a gate electrode and a wire above the gate electrode or between multi-layered wires, a method based on chemical mechanical polishing of a silicon oxide film has come to be used frequently in place of a flattening method using a conventional spin-on-glass (SOG) film.
When the chemical mechanical polishing is adopted to a step of manufacturing an LSI, the quality of the wafer after polishing is an important problem. Representative problems for qualities of wafers after polishing are (1) Scratch, (2) Sticking foreign materials (particles), (3) Uniformity (flatness), and the like.
The (1) scratch is roughly classified into macro scratch and micro scratch. The former is considered to be caused by fall of grinder particles from a diamond dresser used for dressing the polishing pad. The latter is mainly caused by a large agglomerate contained in polishing slurry or clogging of the polishing pad.
In addition, particles contained in the polishing slurry such as grinder particles and a large amount of alkali metal ions remain on the wafer surface after polishing. Therefore, cleaning processing (post cleaning) after polishing must be carried out under sufficient management to remove (2) sticking foreign materials (particles).
In the step of polishing a silicon oxide film as described above, polishing slurry obtained by dispersing silica particles in water is used generally. A hydrophilic silanol group (Sixe2x80x94OH) exists on the surface of silica. Therefore, when silica particles are dispersed in water, cohesion of particles (primary particles) occurs due to the hydrogen bond between particles and the force of van der Waals, so that agglomerates (secondary particles) having a greater grain diameter than a single particle are formed. Therefore, in case of polishing slurry obtained by dispersing silica particles (dispersoid) in water (dispersion medium), the agglomerates constitute components of grinder particles.
The agglomerates do not cause any problem if they have a relatively small grain diameter. However, since some huge agglomerates having a grain diameter of 1 xcexcm or more exist in the polishing slurry in practice, they cause a very small scratch called a micro scratch on the surface of the wafer, thereby to cause lowering of the yield and reliability. Particularly, in the step of forming an element separation groove described above, a thin oxidation-resistant insulating film formed on the wafer surface is used as a stopper for polishing, to polish the silicon oxide film. Therefore, if a micro scratch occurs on the surface of the oxidation-resistant insulating film, it reaches the silicon substrate as a ground layer, causing deterioration in characteristics of the transistor and etching residues during processing of a gate.
As has been described above, micro scratches are mainly caused by agglomerates in polishing slurry. Therefore, the number of agglomerates is reduced, for example, by a method in which an interface acting agent is added to polishing slurry to improve dispersibility of silica particles, a method in which polishing slurry is filtered to remove agglomerates, or the like. However, even this kind of countermeasure is taken, micro scratches may be caused when the polishing condition is changed, e.g., when the lot of the polishing slurry is changed or when the polishing pad is repapered.
As a countermeasure against micro scratches, a proposal has been made of a grinding grain free polishing method which does not contain grinding particles as a component such as silica or the like or the concentration of the grinding component is lowered very much (for example, Japanese Patent Application No. 10-317233). However, since the range to which this method is applicable is limited, polishing slurry containing grinding particles as a component must be used in the current mass-production wafer process.
Consequently, in order to prevent deterioration of the yield and reliability due to micro scratches, occurrence of a micro scratch must be found in a stage which is as early as possible after the chemical mechanical polishing processing, the factor causing the occurrence of the micro scratch must be found, and appropriate polishing conditions must be selected.
However, since micro scratches have a very small size, it is very difficult to detect and check occurrence of a micro scratch immediately after polishing. In most cases, abnormality caused by a micro scratch is found only after several steps or at the time of an inspection on a cross-section which is carried out in the final inspection step of a wafer process. Therefore, there is a problem that a large number of wafers have become defective when a defect caused by a micro scratch is found in the mass-production wafer process in which chemical mechanical polishing is carried out.
An object of the present invention is to provide a technique capable of detecting occurrence of micro scratches in a stage which is as early as possible after chemical mechanical polishing processing in a mass-production wafer process.
Another object of the present invention is to provide a technique capable of detecting micro scratches, without performing a breakdown inspection on product wafers flowing through a mass-production process.
Further another object of the present invention is to provide a technique for evaluating micro scratches, which is matched with mass-production of integrated circuit devices each having a micro pattern.
Further another object of the present invention is to provide a technique of restricting deterioration of the yield and reliability of integrated circuit devices, which is caused by micro scratches.
The above-described objects and other objects of the present invention and novel features thereof will be clearly understood from the description of the present specification and the drawings attached herein.
Schematic of representative one of the inventions disclosed in the present application will be briefly explained as follows.
According to an aspect of the present invention, a method of manufacturing a semiconductor integrated circuit device comprises: a step (a) of forming an insulating film on a main surface of a plurality of first wafers which flow through a mass-production process; a step (b) of preparing a dummy wafer for monitoring, on which a silicon-oxide-based insulating film is formed; a step (c) of performing chemical mechanical polishing processing on the insulating films respectively formed on main surfaces of the plurality of first wafers and the dummy wafer; a step (d) of performing etching processing on the insulating film of the dummy wafer with use of a solution containing hydrofluoric acid, after the step (c) of performing the chemical mechanical polishing processing; and a step (e) of measuring a number of scratches on the insulating film of the dummy wafer subjected to the etching processing, thereby to manage the number of scratches formed in the insulating films of the plurality of first wafers in the step (c) of performing the chemical mechanical polishing processing.
In the present application, the chemical mechanical polishing (CMP) generally means that polishing is carried out, supplying polishing slurry, while the surface to be polished is kept in contact with a polishing pad made of a sheet material such as a soft cloth or the like.
The polishing slurry generally means a suspension liquid in a liquid colloid state in which micro grains of a polishing agent (dispersoid) is mixed in water and a chemical etching agent (dispersion medium). The micro grains of a polishing agent are generally micro grains of silica, ceria, zirconia, alumina, or the like.
The polished flattened insulating film separation grooves mean element separation grooves which are formed in such a manner that an insulating film having a flattened surface is let selectively remain in the grooves. Therefore, element separation grooves which are formed merely by simply depositing an insulating film inside grooves do not meet the polished flattened insulating film separation grooves used herein. For example, element separation grooves generally called SGI (Shallow Groove Isolation) or STI (Shallow Trench Isolation) meet the polished flattened insulating film separation grooves used herein.
In the present application, the mass-production process on a wafer line indicates a case where the throughput of a specific chemical mechanical polishing device used on the wafer line for one day is at least 25 sheets or more, 50 sheets or more, or more generally 100 sheets or more, calculated by 8-inch wafers. Needless to say, this limit number of sheets is in inverse proportion to the area of the wafer.
The dummy wafer or monitor wafer does not means a wafer on which an integrated circuit device as a product is formed (called also a product wafer in the present application) but means a wafer used for determining whether a product wafer which has passed through a specific manufacturing process (e.g., the chemical mechanical polishing step in the present application) is non-defective or defective.
In the embodiment described later, explanation will be divided into a plurality of sections or embodiments if it is necessary for conveniences. Except for the case where a clear indication is specially given, they are related with each other, and there is a relationship that one section or embodiment is a modification, specification, or supplementary explanation of part or all of another section or embodiment.
Further, where the following embodiment deals with a numerical expression (including a number, a numerical value, amount, range, and the like) concerning components, the numerical expression is not limited to the specific number but may be greater or smaller than the specific number, except for the case that a specific indication is given and the case that the expression is apparently limited to a specific number on principles. Further, in the following embodiment, structural components thereof (including componential steps and the like) are not always essential except for the case that a specific indication is given and the case that they are considered to be essential on principles.
Likewise, where the following embodiment deals with the shape of a structural component, positional relationship thereof, or the like, the embodiment covers such a component that is approximate or similar to the shape or the like, except for case that a clear indication is specially given and the case that such a component is apparently considered to be different on principles. This also applies to numerical values and ranges described above.
The semiconductor integrated circuit device used in the present application includes not only components that are formed on a monocrystal silicon substrate but also all other components formed on other substrates, such as an SOI (Silicon On Insulator) substrate, a TFT (Thin Film Transistor) liquid crystal manufacture substrate, and the like, except for the case that a clear denial indication is specially given. In addition, the wafer indicates a monocrystal silicon substrate (generally having a disk-like shape), an SOI substrate, a glass substrate, an insulating or semi-insulating substrate, a semiconductor substrate, or a composite substrate thereof, which is used for manufacturing a semiconductor integrated circuit device.